Daniel Barlow  <dan@telent.net> wrote:
+---------------
| If there's a cpu out there on which doesn't have a type suitable for
| use as a lisp pointer that can be cheaply updated atomically, we
| probably are going to have fun if/when we port to it.  I'm having
| trouble believing that any successful cpu would be that stupid, though.
+---------------

Just to show that it's not unimaginable... Consider a pair of 64-bit CPUs
sharing memory on a 32-bit PCI bus.[1] Let both CPUs be storing a 64-bit
"Lisp value" (pointer) into the same location, when the 32-bit memory
decides it needs to take a breather (for a refresh, or something).
Since PCI *requires* that bus masters accept a "target abort" anywhere
in the middle of a burst and continue the operation from the first word
that didn't transfer, it is quite possible that CPU "A" could store the
first 32 bits of a 64-bit pointer, then the memory "target abort" on
the second 32 bits, then CPU "B" might win the next arbitration and
store all 64 bits of its poitner, then CPU "A" retry the store of its
second 32 bits and succeed this time, leaving the target location garbled.

It *could* happen...


-Rob

[1] A "D32/A64" bus, that is: only 32 data wires, but 64-bit addresses
    provided with dual-cycle address phases (which PCI supports).

-----
Rob Warnock			<rpw3@rpw3.org>
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