Tim Bradshaw <email@example.com> wrote:
| It's not really safe to generalise from a single instance, of course.
| Clearly as the number of cores go up various tradeoffs have to be
| made. Of course, one thing that I don't think Rob mentioned is that
| one thing you can do, *if* you have enough pllism to exploit, is to
| have a large number of cores each clocked relatively slowly. Power
| goes as some quite nasty power of clock speed (2? 4?), so you win
| this way.
Actually, my point was that as transistor geometries get ever smaller,
the leakage current has become a serious source of power dissipation
even when running at *zero* clock speed -- and will continue to grow
even worse, unless something changes drastically, and become a
larger & larger percentage of the total power budget. [Some claim
it's *already* as much as 50% of the power!]
 I'm not sure the recent announcements by Intel & IBM on "high-K"
dialectrics counts as a "drastic" change, though it certainly has
the possibility to push back the "leakage wall" a little bit longer.
Rob Warnock <firstname.lastname@example.org>
627 26th Avenue <URL:http://rpw3.org/>
San Mateo, CA 94403 (650)572-2607