allegro-cl archives 1999-12-9 | home index prev H thread prev K thread next J next L |
From: Shiv Subject: (:explain :variables) Date: 1999-12-9 15:27 I have been trying to get ACL5.0 (Solaris) to allocate some floating-point variables in registers. Unfortunately I could not find a small example of my problem. Here is what the (:explain :variables) decalaration gives: Variables stored in registers: (A-1D I J I ISTART ISTART J JSTART IINDEX #:G3544 JINDEX) Variables stored in floating point registers: (S C TAU0 TAU1 C S #:G3549 #:G3552) ^ ^ ^ ^ The variables S and C are the problem. From above I thought they were in registers, but looking at the disassembled output shows they are not! Is there anyway I can make c & s to be stored in floating-point registers? There are plenty around! Thanks, --shiv-- Here is the function: (defun givens-rotate-rows-submatrix (A-1D i j c s displaced-to-column first-outside-column no-of-columns-of-parent) "Applies the givens rotation corresponding to (c,s) to rows i and j from column displaced-to-column for no-of-columns-of-submatrix." (declare (single-float c s) (fixnum i j displaced-to-column first-outside-column no-of-columns-of-parent) (type (simple-array single-float (*)) A-1D) (optimize (speed 3) (safety 0) (space 0) (debug 0)) (:explain :variables)) (loop with (tau0 tau1) single-float with istart fixnum = (the fixnum (* no-of-columns-of-parent i)) with jstart fixnum = (the fixnum (* no-of-columns-of-parent j)) for iindex fixnum from (+ istart displaced-to-column) below (+ istart first-outside-column) for jindex fixnum from (+ jstart displaced-to-column) do (setf tau0 (aref A-1D iindex) tau1 (aref A-1D jindex) (aref A-1D iindex) (- (* c tau0) (* s tau1)) (aref A-1D jindex) (+ (* s tau0) (* c tau1))))) and here is the disassembled output (I have added the comment line "not in register"): USER(61): (disassemble 'givens-rotate-rows-submatrix) ;; disassembly of #<Function GIVENS-ROTATE-ROWS-SUBMATRIX> ;; formals: A-1D I J C S DISPLACED-TO-COLUMN FIRST-OUTSIDE-COLUMN NO-OF-COLUMNS-OF-PARENT ;; code start: #x894d854: 0: 9de3bf88 save %o6, #x-78, %o6 4: fd072002 ld [%i4 + 2], %f30 8: f906e002 ld [%i3 + 2], %f28 12: fd27bff0 st %f30, [%i6 + -16] 16: fd013d3b ld [%g4 + -709], %f30 ; FLOAT_0 20: f927bfe8 st %f28, [%i6 + -24] 24: f9013d3b ld [%g4 + -709], %f28 ; FLOAT_0 28: c407a064 ld [%i6 + 100], %g2 32: 9138a002 sra %g2, #x2, %o0 36: 92100019 mov %i1, %o1 40: dc213efb st %o6, [%g4 + -261] 44: de0122b7 ld [%g4 + 695], %o7 ; %MUL 48: 9fc3e000 jmpl %o7 + 0, %o7 52: 86182002 xor %g0, #x2, %g3 56: c8213efb st %g4, [%g4 + -261] 60: a0100008 mov %o0, %l0 64: c407a064 ld [%i6 + 100], %g2 68: 9138a002 sra %g2, #x2, %o0 72: 9210001a mov %i2, %o1 76: dc213efb st %o6, [%g4 + -261] 80: de0122b7 ld [%g4 + 695], %o7 ; %MUL 84: 9fc3e000 jmpl %o7 + 0, %o7 88: 86182002 xor %g0, #x2, %g3 92: c8213efb st %g4, [%g4 + -261] 96: cc07a05c ld [%i6 + 92], %g6 100: 98040006 add %l0, %g6, %o4 104: cc07a060 ld [%i6 + 96], %g6 108: 96040006 add %l0, %g6, %o3 112: cc07a05c ld [%i6 + 92], %g6 116: 90020006 add %o0, %g6, %o0 120: 80a3000b cmp %o4, %o3 124: 26800009 bl,a 160 128: 9406000c add %i0, %o4, %o2 132: 90100004 mov %g4, %o0 lb1: 136: 86102001 mov #x1, %g3 140: 81c7e008 jmp %i7 + 8 144: 91ea0000 restore %o0, %g0, %o0 148: 10800003 ba 160 152: 9406000c add %i0, %o4, %o2 lb2: 156: 9406000c add %i0, %o4, %o2 lb3: 160: fd02a002 ld [%o2 + 2], %f30 164: 94060008 add %i0, %o0, %o2 168: f902a002 ld [%o2 + 2], %f28 172: f507bfe8 ld [%i6 + -24], %f26 ; not in register 176: b1a6893e fmuls %f26, %f30, %f24 180: ed07bff0 ld [%i6 + -16], %f22 ; not in register 184: a9a5893c fmuls %f22, %f28, %f20 188: b1a608b4 fsubs %f24, %f20, %f24 192: 9406000c add %i0, %o4, %o2 196: f122a002 st %f24, [%o2 + 2] 200: bda5893e fmuls %f22, %f30, %f30 204: b9a6893c fmuls %f26, %f28, %f28 208: bda7883c fadds %f30, %f28, %f30 212: 94060008 add %i0, %o0, %o2 216: fd22a002 st %f30, [%o2 + 2] 220: 98032004 add %o4, #x4, %o4 224: 80a3000b cmp %o4, %o3 228: 36bfffe9 bge,a 136 232: 90100004 mov %g4, %o0 236: 10bfffec ba 156 240: 90022004 add %o0, #x4, %o0 USER(62): |